(1) Field of the Invention
This invention relates to a solid-state imaging device which reads out photo information stored in a plurality of photodiodes arrayed in one dimension or two dimensions in the surface region of a semiconductor body. More particularly, it relates to improvements in a signal processing circuit of the solid-state imaging device.
(2) Description of the Prior Art
The construction of a prior-art solid-state imaging device is schematically shown in FIG. 1A.
FIG. 1A illustrates an example of the principle construction of a solid-state area sensor (imaging device), while FIG. 1B illustrates an example of a pulse timing chart of horizontal scanning pulses and vertical scanning pulses. In FIG. 1A, numerals 1 and 2 designate horizontal and vertical scanning circuits respectively. By applying clock pulses CP.sub.x and CP.sub.y ordinarily of two to four phases, the respective scanning circuits supply output lines of their stages 7 and 8 or lines O.sub.x(1), O.sub.x(2) . . . and O.sub.y(1), O.sub.y(2) . . . with output pulses V.sub.ox(1), V.sub.ox(2) . . . and V.sub.oy(1), V.sub.oy(2) . . . shown in FIG. 1B into which input pulses V.sub.sx and V.sub.sy have been shifted by fixed timing intervals of the corresponding clocks. Using the output pulses, switching elements 5 and 6 are turned "on" and "off" one by one, to fetch at a video output terminal 4 signals from individual photoelectric conversion elements 3 arrayed in two dimensions. Since the signals from the photoelectric conversion elements correspond to an optical image of an object projected on these elements, video signals can be fetched by the above operation.
In order to attain a high resolution, the solid-state imaging device of this type requires photoelectric conversion elements and switching elements in numbers of about 500.times.500 and scanning circuits each having a plurality of stages. Therefore, it is usually fabricated by the use of the MOS-VLSI technology with which a high packaging density is realized comparatively easily and with which the photoelectric conversion element and the switching element can be formed as a unitary structure. FIG. 2 shows the structure of a picture element which occupies most of the area of a sensor IC. Numeral 13 designates a semiconductor body (such as semiconductor substrate, epitaxial grown layer and well diffused region) of one conductivity type. Numerals 5 and 6 designate switching elements, respectively, which are made of insulated-gate field effect transistors (hereinbelow, termed "MOS transistors") for addressing horizontal and vertical positions. They are constructed of diffused layers 14, 15 and 16 having the opposite conductivity type to that of the body 13 and forming drains and sources, and gate electrodes 18 and 19 disposed through an insulating film 17. The layer 14 also constitutes a photodiode which utilizes the source of the MOS transistor 6 serving as the vertical switching element. Charges in a quantity having been discharged in proportion to incident photons are given from a voltage source for a video output 11 into the diode 14 in a position in which output pulses V.sub.ox(N) and V.sub.oy(N) of respective scanning circuits 1 and 2 utilizing, for example, shift registers made up of MOS transistors are simultaneously applied to the gates of the switching MOS transistors through output lines O.sub.x(N) and O.sub.y(N) of the scanning circuits. A charging current at that time is read out from a signal output terminal 4 through a load resistance 12 as a video signal.
With such prior-art device, however, fixed pattern noise occur due to a cause to be stated below and form a fatal drawback of the photosensor.
FIG. 3A depicts the structure of FIG. 2 more simply. Numeral 13 designates a semiconductor body, for example, Si body of the P-type conductivity, and numeral 14 one photodiode which is formed of a diffusion layer of the N.sup.+ -type conductivity. A region 15 corresponds to the vertical signal output line 9 shown in FIG. 1A, and a region 16 to the horizontal signal output line 10 shown in FIG. 1A. The region 15 in FIG. 3A may well be divided into two regions of the drain of a MOS transistor 6 and the source of a MOS transistor 5, the subregions being connected with a metal such as aluminum.
FIGS. 3B to 3F illustrate channel potentials corresponding to FIG. 3A. Now that the N channel type devices are considered, the potential has its plus direction taken downwards.
In the state of FIG. 3B, signal charges 31 are stored in the photodiode 14, and 0 (zero) V is applied to the gate 18 of the vertical switching MOS transistor (hereinbelow, abbreviated to "VTr") 6 and the gate 19 of the horizontal switching MOS transistor (hereinbelow, abbreviated to "HTr") 5, so that both the transistors are "off".
FIG. 3C shows the state in which the VTr 6 turns "on", and the signal charges spread underneath the gate 18 of the VTr 6 and into the vertical signal output line 15. FIG. 3D illustrates the potentials at the time when the HTr 5 is also turned "on", and the signal charges are spreading also into the horizontal signal output line 16 and are being delivered therefrom. FIG. 3E illustrates the state in which the signal charges have been once read out, and the respective potentials have been reset to V.sub.o. In FIG. 3F, the HTr 5 turns "off", and the signal of the next picture element is being read out.
As understood from FIGS. 3E and 3F, some 32 of the signal charges are left under the gate 19 of the horizontal switching MOS transistor HTr 5, and they are delivered from under the gate to the horizontal output line 16 when the horizontal scanning pulse turns "off".
FIG. 4A shows a shift register which consists of inverters 41 and transfer gates 42 and which has heretofore been well known.
The shift register in FIG. 4A is a prior-art example of a horizontal scanning circuit. As illustrated in a pulse timing chart of FIG. 4B, in the prior-art device, the time at which the n-th horizontal scanning pulse V.sub.ox(n) turns "off" and the time at which the ensuing (n+1)-th horizontal scanning pulse V.sub.ox(n+1) turns "on" are determined by the same trigger pulse of a horizontal clock pulse .phi..sub.x2.
More specifically, the time at which the horizontal scanning pulse V.sub.ox(n+1) turns "on" is the time at which the signal of the (n+1)-th column is provided, and it is also the time at which the horizontal scanning pulse V.sub.ox(n) of the n-th column turns "off". In sum, in the prior-art device, as seen from FIGS. 3E and 3F, some Q.sub.R 32 of the signal charges of the photodiode of the n-th column having been trapped under the gate 19 of the horizontal switching MOS transistor 5 of the n-th column are delivered at the time when the signal of the photodiode of the (n+1)-th column is delivered. If the residual charges Q.sub.R are equal in all the columns, there will be no problem. However, when they are unequal, they form one cause for the fixed pattern noise.
As a result, normal video signals are not obtained in the solid-state imaging device, and vertical stripes appear on a reproduced picture screen, which spoils the picture quality seriously.